1. Technical Field
Various embodiments relate to a semiconductor integrated circuit, and more particularly, to a clock generation circuit.
2. Related Art
A semiconductor integrated circuit is designed to operate in synchronization with a clock which is inputted from an outside. Research has been continuously conducted to improve the operation speed of a semiconductor integrated circuit, and currently, a semiconductor integrated circuit is designed to operate by receiving a clock with a high frequency.
However, test equipment for testing a semiconductor integrated circuit operates using a clock with a frequency lower than the semiconductor integrated circuit.
Therefore, a semiconductor integrated circuit is designed such that, in a test, the semiconductor integrated circuit receives a clock with a low frequency, generates a clock with a high frequency and uses the generated clock in an operation of the semiconductor integrated circuit.
Referring to FIG. 1, a conventional clock generation circuit includes a first frequency division unit 10, a frequency comparison unit 20, a charge pump 30, a voltage control oscillator 40, and a second frequency division unit 50.
The first frequency division unit 10 divides an input clock CLK_in and generates a reference clock CLK_ref.
The frequency comparison unit 20 compares the frequencies of the reference clock CLK_ref and a feedback clock CLK_fb, and generates a frequency comparison signal Fre_com.
The charge pump 30 generates a charge pumping voltage V_cp in response to the frequency comparison signal Fre_com.
The voltage control oscillator 40 generates an output clock CLK_out in response to the voltage level of the charge pumping voltage V_cp.
The second frequency division unit 50 divides the output clock CLK_out and generates the feedback clock CLK_fb.
The conventional clock generation circuit configured in this way determines the frequency of the output clock CLK_out according to the division ratios of the first frequency division unit 10 and the second frequency division unit 50 (the division ratio of the second frequency division unit 50/the division ratio of the first frequency division unit 10). For example, when assuming that the first frequency division unit 10 generates the reference clock CLK_ref by dividing by 5 the frequency of the input clock CLK_in and the second frequency division unit 50 generates the feedback clock CLK_fb by dividing by 10 the frequency of the output clock CLK_out, the frequency of the output clock CLK_out becomes two times the frequency of the input clock CLK_in.
However, in the conventional clock generation circuit, the voltage level of the charge pumping voltage V_cp is raised and lowered in response to information on a frequency difference between the input clock CLK_in and the output clock CLK_out. In addition, the frequency of the output clock CLK_out is determined according to the voltage level of the charge pumping voltage V_cp. That is to say, in the conventional clock generation circuit, since the frequency difference is converted into the type of an analog voltage and the frequency of the output clock CLK_out is determined according to the level of the analog voltage, if the voltage level of the charge pumping voltage V_cp changes according to a voltage level variation of a driving voltage used in the conventional clock generation circuit, the frequency of the output clock CLK_out is likely to be influenced.